// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// PROGRAM		"Quartus II 64-Bit"
// VERSION		"Version 13.1.0 Build 162 10/23/2013 SJ Full Version"
// CREATED		"Sun Nov 18 22:30:02 2018"

module lab1_4(
	add_sub,
	cin,
	clk,
	a,
	b,
	overflew,
	result
);


input wire	add_sub;
input wire	cin;
input wire	clk;
input wire	[63:0] a;
input wire	[63:0] b;
output wire	overflew;
output wire	[63:0] result;






lpm_add_sub0	b2v_inst(
	.cin(cin),
	.add_sub(add_sub),
	.clock(clk),
	.dataa(a),
	.datab(b),
	.cout(overflew),
	.result(result));


endmodule
